17607506214
Fail-safe input
Programmable output slew rate control
The CDCDB800 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB800 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB800 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.
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